1. Field of the Invention
The present invention relates to a verification circuit, or comparison and decision circuit for comparing a data written in RAM with a data written in and read from a PROM whereby verification of the data is made.
2. Prior Art
A prior verification circuit is described with reference to FIG. 4.
The verification circuit comprises a CPU 1, a RAM 2 storing a data A composed of 2 bits and connected with an output of the CPU 1, an input of an I/O port 3 connected with the output of the CPU 1 and an output of the RAM 2, a PROM 4 connected with the output of the RAM 2 via the I/O port 3, the data A being written in the PROM 4, a plurality of, comparators 5 input terminals thereof respectively connected with the output of the PROM 4 and outputs of reference voltage 6 having H and L levels (for example the former is set to 2.35 V and the latter to 0.5 V) via a switch 7.
With such an arrangement, the prior verification circuit is operated as follows,
reading a data A composed of "1" and "0" stored in the RAM 2 by CPU 1 based on an instruction from the CPU 1, PA1 transferring the read data A to the PROM 4 through the I/O port 3, PA1 writing the data A in the PROM 4 which is called as the data B, (the data B is same as the data A. To verify the data A is correct or not, it is troublesome to compare the data A with data A. Therefore, for convenience of comparison and verification the data stored in the RAM 2 is called as the data A and the data A written in the PROM 4 is called as the data B), PA1 reading the data B composed of "1" and "0" from the PROM 4 by the CPU 1 according to the instruction from the CPU 1, every time the clock pulse is issued and the data A is written in the PROM 4, PA1 switching the switch 7 to issue the reference voltage of H level thereof to decide as to whether the data B is "1" or not, PA1 switching the switch 7 to issue the reference voltage of L level thereof to decide as to whether the data B is "0" or not, PA1 verifying by CPU 1 as to whether the data A is identical with a result of comparison between the data A and the data B.
However, there are the following problems in the prior verification circuit. Firstly, the reference voltage is changed to H or L level every time deciding as to whether the data B is H or L level; secondly, a verification of the data A read from the RAM 2 and the data B read from the PROM 4 is made by the CPU 1. As result, there occurred a problem that the time to verify the data A can not be reduced.